Modern microprocessors may be implemented so that ISA instructions and their constituent components (e.g., micro-operations) are organized into transactions. The transactions have multiple sub-components that are executed by the processor. The individual transactions as a whole appear atomic and indivisible even if the sub-components are executed independently internally. Prior to commitment of a transaction, the sub-component operations can speculatively affect the cache subsystem (e.g., via a speculative store). Regardless of how transactional memory is handled, a multi-threaded processor increases the complexity of maintaining the coherency of the data cache because cache locations typically are shared by the processing threads. These processors must ensure that speculative data from one thread is not visible to another thread. Alternatively, if speculative data from one thread has become visible to another, a rollback on one thread requires a coordinated rollback of any other thread that has observed the speculative data.